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cpu
- 基于十二条简单汇编指令构成的一个cpu 采用vhdl语言编写 内附源代码 工具sylinx-Based on 12 simple assembly instructions consisting of a cpu using vhdl language source code tool sylinx included
FPGA-cpu
- 基于FPGA的简易处理器设计2010/05/04-A simple FPGA-based processor design 2010/05/04
mips
- MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
PipelineCPU
- Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
cpu86
- this is a vhdl implementation of cpu 86
CPU
- Cpu with 8 bits in VHDL verilog Code
CPU
- VHDL16位cpu，能实现加减法移动等指令-vhdl 16 cpu,include add,sub,move and so on.
CPU_marjan
- a core of cpu that the of it,is marjan
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
cpu
- 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
cpu
- 基本功能的cpu，自定义内存内容~了解CPU运作原理~-design of cpu,VHDL environment~
simple-16b-cpu-vhdl-code
- vhdl source code for simple cpu
Perfect_CPU
- CPU硬件,才用10条语句的指令。这是清华大学的一个作业题-cpu
16位CPU设计
- 给定指令系统的处理器设计，VHDL语言，包括代码和仿真波形
cpu-leon3-altera-ep1c20
- CPU性能仿真测试软件，对于VHDL设计的芯片可以做新能测试-CPU VHDL
CPU-VHDL
- cpu pipeline processing
MCPU
- 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
eetop.cn_RISC32 VHDL
- 根据vhdl设计的32位CPU具备加减 读写等标准功能(a 32-bit cpu based on VHDL designed with function of fundamental function of subtraction , addition, load and store .)